1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing methods thereof. Particularly, the present invention relates to a semiconductor device having an impurity concentration profile applied to a contact region between a semiconductor substrate and a conductive layer, and a manufacturing method thereof.
2. Description of the Background Art
In accordance with the recent significant increase in the integration density of a semiconductor integrated circuit device, microminiaturization of elements has evolved rapidly. Particularly in a dynamic random access memory (DRAM) which is one semiconductor memory device, the integration density of the memory is increased corresponding to increase in the storage capacity such as from 64 megabits to 256 megabits, and further to 1 gigabit. Field effect transistors and capacitors functioning as active elements constituting a highly integrated memory must have miniaturized structures. The diameter of the contact with the impurity region of a semiconductor substrate is also reduced corresponding to miniaturization of the active elements.
The leakage current flowing from the contact to the semiconductor substrate will result in a great amount in one semiconductor device as the number of contacts formed in one device becomes greater in association with the integration of the active elements. In forming a highly integrated semiconductor device, the ratio of the leakage current to the entire power consumption will take a great value. Furthermore, there is a problem that the operating voltage of an active element, for example a field effect transistor, will be limited due to a lower junction breakdown voltage at the contact caused by increase in the impurity concentration of the semiconductor substrate by scaling of active elements.
FIG. 21 is a partial sectional view of a conventional contact structure. As shown in FIG. 21, an n type impurity region 106 including n type impurities is formed having a predetermined depth from the surface of a p type silicon substrate 101. A contact hole 116 is formed in an interlayer insulation film 115 so as to expose the surface of n type impurity region 106. A conductive layer 110, for example an electrode layer, a storage node of a capacitor, is formed so as to come into contact with the surface of n type impurity region 106 through contact hole 116.
In the above contact structure, ions for preventing leakage current are implanted, if necessary, after contact hole 116 is formed. Then, a conductive material such as polycrystalline silicon having n type impurities doped is introduced into contact hole 116 to form conductive layer 110.
FIG. 22 shows the impurity concentration profile at the position of XXII of FIG. 21. As shown in FIG. 22, silicon substrate 101 has an impurity concentration profile p(B) in which boron (B) is introduced as the p type impurity. N type impurity region 106 has an impurity concentration profile n(P) in which phosphorus (P) is introduced as the n type impurity. The junction point J where the curves of these two impurity concentration profiles cross each other has a concentration of approximately 1xc3x971017cmxe2x88x923.
At the region of the silicon substrate including the above-described impurity concentration profile, a p type impurity region for adjusting the threshold voltage of a field effect transistor and a p type impurity region for preventing inversion, formed at a region beneath an element isolation insulation film, are formed so as to extend over an element formation region. In this case, the p type impurity concentration increases at shallow regions in the p type impurity concentration profile p(B). The position of junction point J is shifted towards a higher impurity concentration. When a voltage is applied to conductive layer 110, a depletion layer cannot easily spread since the impurity concentration is great at the pn junction to induce the possibility of electric field concentration. Particularly, the problem of reduction in the junction breakdown voltage due to increase in the impurity concentration at the pn junction is noted. There was also the problem of a greater leakage current in the contact structure due to increase in the impurity concentration at the pn junction.
U.S. patent application Ser. No. 08/709,592 discloses a contact structure for preventing reduction in the junction breakdown voltage and increase in leakage current.
FIG. 23 is a partial sectional view of a contact structure disclosed in the aforementioned application. Referring to FIG. 23, a p type well formation dope region 103, a p type channel cut region (inversion prevention region) 104, and a p type channel dope region 105 (for adjusting threshold voltage) with respective predetermined depth are formed at a p type silicon substrate 101. An n type impurity region. 106 is formed at p type silicon substrate 101. A contact hole 116 exposing the surface of n type impurity region 106 is formed in an interlayer insulation layer 115. A conductive layer 110 is formed so as to come into contact with the surface of n type impurity region 106 via contact hole 116.
FIG. 24 shows an impurity concentration profile at a position XXIV of FIG. 23. As shown in FIG. 24, a p type impurity concentration profile p(B) includes impurity concentration peaks respectively corresponding to p type well formation dope region 103, p type channel cut region 104, and p type channel dope region 105. An n type impurity concentration profile n(P)exhibits values higher than the respective impurity concentrations of p type channel cut region 104 and p type channel dope region 105 at predetermined depth thereof. N type impurity concentration profile n(P) has a junction point J in the proximity of a minimum value X of p type impurity concentration profile p(B).
As described above, the position of the pn junction is located at a low impurity concentration level in both the n type impurity concentration profile n(P) and p type impurity concentration profile p(B). Therefore, in comparison to the case where junction point J is located at a high impurity concentration level, the depletion layer is easily depleted to exhibit a greater expansion even when the voltage applied to conductive layer 110 is identical. The junction does not break down until the voltage applied to the contact becomes higher. Therefore, the junction breakdown voltage is improved. As a result, the electric field generated at the pn junction is mitigated to reduce the leakage current generated at the contact region.
FIG. 25 is a partial sectional view of a memory portion of a DRAM in which an impurity concentration profile as shown in FIG. 24 is applied. Referring to FIG. 25, a gate electrode 109 is formed on a p type silicon substrate 101 with a gate insulation film 108 thereunder. A pair of n type source/drain regions 106 and 107 are formed at a surface region of silicon substrate 101 at both sides of gate electrode 109. A storage node 110 is formed so as to come into contact with the surface of one source/drain region 106. A dielectric film 111 is formed so as to cover the surface of storage node 110. A cell plate 112 is formed so as to cover the surface of dielectric film 111. A capacitor is formed of storage node 110, dielectric film 111, and cell plate 112. A bit line 113 is formed so as to come into contact with the other source/drain region 107. Storage node 110 comes into contact with n type source/drain region 106 through a contact hole 116 formed in an interlayer insulation film 115. N type source/drain region 106 is formed of a region into which arsenic (As) is introduced, and a region including phosphorus (P) provided to improve the breakdown voltage of the pn junction and to suppress leakage current, as described above.
FIG. 26 shows the impurity concentration profile at a position XXVI of FIG. 25. As shown in FIG. 26, a p type impurity concentration profile p(B) has respective impurity concentration peaks corresponding to p type well formation dope region 103, p type channel cut region 104, and p type channel dope region 105. An n type impurity concentration profile n(P) exhibits an impurity concentration at the position between p type channel cut region 104 and p type channel dope region 105 higher than respective values thereat. N type impurity concentration profile n(P) has a pn junction point J in the proximity of a minimum value X of p type impurity concentration profile p(B). Thus, the junction breakdown voltage is improved, and the leakage current due to electric field mitigation is reduced. In FIG. 26, an n type impurity concentration profile n(As) in which arsenic (As) is introduced to form the original source/drain region is also shown.
In the memory portion of a DRAM having an impurity concentration profile as shown in FIG. 26, miniaturization of the field effect transistor is advanced according to increase of the storage capacity. In a DRAM having a memory capacity of approximately 1 gigabit, the gate has a length L of approximately 0.15 xcexcm in the field effect transistor shown in FIG. 25. The distance D between the sidewall of contact hole 116 and the sidewall of gate electrode 109 becomes as small as 0.075 xcexcm. In accordance with miniaturization of a field effect transistor, p type channel dope region 105 is formed so as to have a shallow and abrupt concentration gradient in FIG. 26. Therefore, as shown by the arrow in FIG. 26, n type source/drain region 106 is formed to have an n type impurity concentration profile n(P) exhibiting a higher impurity concentration at the shallow region. As a result, the region of n type source/drain region 106 where phosphorus (P) is introduced to mitigate the electric field and to improve the junction breakdown voltage is formed so as to have a higher concentration at the shallow region and to spread laterally as indicated by the chain line with two dots in FIG. 25.
The formation of the above n type source/drain region 106 induces problems set forth in the following.
The lateral spread of n type source/drain region 106 indicated by the chain line with two dots in FIG. 25 causes the field effect transistor to be easily turned on at a threshold voltage lower than that of the designed value. In other words, the characteristic of the field effect transistor is altered. For example, the threshold voltage is reduced. As a result, electrons of storage node 110 will easily leak out.
Also, alteration in distance D in FIG. 25 causes variation in the level of the effect of the spread of n type source/drain region 106 indicated by the chain line with two dots on the characteristics of the field effect transistor. This means that the characteristics of the field effect transistor is altered by variation in the position of contact hole 116. Therefore, the characteristics of the field effect transistor is altered by variation in the step of forming contact hole 116 and the manufacturing process conditions. In other words, the characteristics of the field effect transistor is susceptible to the variation in the formation position of storage node 116.
An object of the present invention is to provide an impurity concentration profile that allows improvement of the breakdown voltage of the pn junction while mitigating the electric field to reducte leakage current without deteriorating the characteristics of a field effect transistor.
Another object of the present invention is to improve pn junction breakdown voltage at a contact of the storage node side of a DRAM, and to mitigate the electric field to reduce leakage current without deteriorating the characteristic of a field effect transistor.
A further object of the present invention is to easily form an impurity concentration profile that allows improvement of pn junction breakdown voltage, and mitigation of the electric field to reduce leakage current without deteriorating the characteristic of a field effect transistor.
A semiconductor device according to an aspect of the present invention includes a semiconductor substrate of a first conductivity type with a main surface, and an impurity region of a second conductivity type formed to have an impurity concentration profile of the second conductivity type extending from the main surface of the semiconductor substrate in the direction of the depth. The semiconductor substrate has an impurity concentration profile of the first conductivity type extending from the main surface in the direction of depth. The first conductivity type impurity concentration profile includes a first maximum point of an impurity concentration at a first depth from the main surface, a second maximum point of an impurity concentration at a second depth that is deeper than the first depth, and a low concentration region indicating an impurity concentration lower than the first and second maximum points at a region deeper than the second depth. The second conductivity type impurity concentration profile forms a junction point at the low concentration region crossing the first conductivity type impurity concentration profile, and includes a second conductivity type impurity concentration at a region from the main surface to the junction point, higher than the impurity concentration indicated by the first conductivity type impurity concentration profile. The second conductivity type impurity concentration profile has a minimum point or an inflection point at a region between the first depth and the second depth.
In the semiconductor device having the above-described structure, the second conductivity type impurity concentration profile forms a junction point crossing the first conductivity type impurity concentration profile at a region of a lower impurity concentration. Therefore, the pn junction breakdown voltage can be improved, the electric field mitigated, and the leakage current reduced. In the semiconductor device of the present invention, the second conductivity type impurity concentration profile has a second conductivity type impurity concentration higher than the impurity concentration indicated by the first conductivity type impurity concentration profile in a region from the main surface to the junction point, and a minimum point or an inflection point at a region between the first depth and the second depth. The presence of this minimum point or inflection point provides the advantage of suppressing the effect of the second conductivity type impurity concentration profile having a higher impurity concentration on the gate electrode formation region of the field effect transistor. As a result, the characteristics of the field effect transistor will not change. For example, the threshold voltage of the field effect transistor will not be reduced.
According to a semiconductor device of the present aspect, the first conductivity type impurity concentration profile preferably includes a third maximum point of an impurity concentration at a third depth deeper than the junction point.
Furthermore, the second conductivity type impurity concentration profile preferably includes a first maximum point of the impurity concentration in the proximity of the first depth, and a second maximum point of the impurity concentration in the proximity of the second depth.
In this case, the first and second maximum points of the second conductivity type impurity concentration profile preferably have an impurity concentration respectively greater than the first and second maximum points of the first conductivity type impurity concentration profile.
Accordingly, an impurity concentration profile can easily be formed that allows improvement of the breakdown voltage at the pn junction and that allows mitigation of the electric field without adversely affecting the characteristics of the field effect transistor.
Further preferably, the first, second, and third maximum points of the first conductivity type impurity concentration profile indicate respective peak concentrations of the impurity region for adjusting the threshold voltage of the field effect transistor, the impurity region for preventing inversion, and the impurity region for forming a well.
Further preferably, a semiconductor device according to an aspect of the present invention includes a field effect transistor. The field effect transistor includes a gate electrode, and first and second source/drain regions of the second conductivity type. The gate electrode is formed above the main surface of the semiconductor substrate with a gate insulation film thereunder. The first and second source/drain regions are formed at the main surface of the semiconductor substrate at both sides of the gate electrode. The first source/drain region includes the above second conductivity type impurity region. Also, the semiconductor device includes a conductive layer formed so as to come into contact with the first source/drain region.
In a semiconductor device of the above-described structure, the characteristics of the field effect transistor is not susceptible to the impurity concentration profile of the first source/drain region to result in variation in the characteristics of the field effect transistor. For example, the threshold voltage of the field effect transistor will not be reduced. As a result, electrons in the conductive layer formed in contact with the first source/drain region, for example in the storage node of a capacitor, is prevented from leaking.
In the semiconductor device of the above-described structure, influence of the second conductivity impurity concentration profile on the field effect transistor due to variation in the position of the contact hole for forming a conductive layer in contact with the first source/drain region is suppressed. Therefore, the characteristics of the field effect transistor will not be altered by variation in the manufacturing process.
The semiconductor device of the above-described structure preferably includes an impurity region for adjusting the threshold voltage at a region of the semiconductor substrate below the gate electrode. The peak concentration of this impurity region corresponds to the first maximum point of the first conductivity type impurity concentration profile.
The above conductive layer preferably constitutes the electrode of a capacitor formed so as to come into contact with the first source/drain region.
The semiconductor device of the above-described structure preferably includes an element isolation insulation film for electrically isolating the field effect transistor, and an impurity region for preventing inversion at a region of the semiconductor substrate beneath the element isolation insulation film. The peak concentration of the impurity region corresponds to the second maximum point of the first conductivity type impurity concentration profile.
A method of manufacturing a semiconductor device according to another aspect of the present invention includes the following steps.
(a) Forming an element isolation insulation film at a main surface of a semiconductor substrate of a first conductivity type.
(b) A first implantation step of ion-implanting impurities of the first conductivity type at a first dose from the main surface to a first depth so as to form an impurity region of the first conductivity type for preventing inversion at a region of the semiconductor substrate beneath the element isolation insulation film.
(c) A second implantation step of ion-implanting impurities of the first conductivity type at a second dose to a second depth smaller than the first depth so as to form an impurity region of first conductivity type for adjusting the threshold voltage at a region of the semiconductor substrate between the element isolation insulation films.
(d) Forming a gate electrode at a region of the semiconductor substrate between the element isolation insulation films with a gate insulation film thereunder.
(e) Forming first and second source/drain regions of a second conductivity type at a main surface of the semiconductor substrate at both sides of the gate electrode.
(f) A third implantation step of ion-implanting impurities of the second conductivity type at a third dose attaining an impurity concentration higher than that by the first dose at the neighborhood of the first depth from the surface in the first source/drain region.
(g) A fourth implantation step of ion-implanting impurities of the second conductivity type at the fourth dose attaining an impurity concentration higher than that by the second dose at the neighborhood of the second depth from the main surface at the first source/drain region.
In the above method of manufacturing a semiconductor device of the present invention , an impurity concentration profile can easily be realized that can improve the pn junction breakdown voltage and mitigate the electric field, and that does not adversely affect the characteristics of the field effect transistor, without using any complicated manufacturing process.
The method of manufacturing a semiconductor device according to the present aspect further includes a fifth implantation step of ion-implanting impurities of the first conductivity type at a third depth deeper than the first depth so as to form a well region of the first conductivity type, prior to the first implantation step.
The above method of manufacturing a semiconductor device can further include a step of forming a conductive layer so as to come into contact with the first source/drain region.
The third and fourth implantation steps of the above method of manufacturing a semiconductor device are preferably effected by ion-implanting impurities through a contact hole formed so as to expose the surface of the first source/drain region.
According to the semiconductor device of the present invention, an impurity concentration profile can be implemented that allows improvement in the breakdown voltage of the pn junction, and that allows reduction of the leakage current by mitigating the electric field. The characteristic of the field effect transistor is not deteriorated by that impurity concentration profile. For example, a threshold voltage as designed can be maintained. As a result, leakage is suppressed of electrons from the storage node connected to the source/drain region. Furthermore, the characteristics of the electric field transistor will not be altered by variation in the position of the contact hole that forms contact with the source/drain region. This means that the characteristic of the field effect transistor is not altered by variation in the conditions of the manufacturing process.
According to a method of manufacturing a semiconductor device of the present invention, the above impurity concentration profile can easily be realized without employing a complicated manufacturing process.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.